Different types of output stages1
- Open Collector
ADC / DAC
Universal Asynchronous Receiver Transmitter
Universal Asynchronous Receiver Transmitter (UART) is an asynchronous serial communication protocol that allows full-duplex communication between only two sides. As there is no clock signal line and only a receive and transmit line on each side, both parties have to agree upon a clock rate and need to have clocks running at ideally exactly the same rate to maintain the synchronization. This makes it difficult to implement UART in both, hardware and software. The rate of an UART transmission is typically specified by the baud rate. It differs from its real bit rate because UART has an overhead of three bits for every eight bits transferred. As a rule of thumb it can be said that today’s ICs should support baud rates of 230400 b/s, but higher rates may be possible and have to be tested. UART is typically used to upload the compiled binary firmware to the MCU, and to send program output or log messages to a computer where it is printed to a serial console. Therefore, usually a USB-to-serial converter is utilized.
Serial Peripheral Interface
Serial Peripheral Interface (SPI) is a synchronous serial communication protocol that only allows one master and basically needs four wires; two lines for full-duplex communication that are called “master out slave in (MOSI)” and “master in slave out (MISO)”, one clock signal (CLK or SCK) and one “slave select (SS)” line that is also often called “chip select (CS)”. Depending on the way how the slaves are connected, the MOSI and MISO lines are either connected in series and the slaves share a common SS line, or all slaves are connected to MOSI and MISO and need an individual SS line each. The dedicated clock line and the full-duplex communication allow very fast clock rates upwards of 10 MHz (thus, 10 Mb/s), that are needed for the interaction with small-sized external flash memory, radio transceivers or high-performance sensors.
I2C is a synchronous bus-based serial communication protocol with which one or even multiple master devices can communicate with multiple slave devices. It requires only two wires, one is used for the clock signal (SCL) generated by a master, and one for the data line (SDA), on which master and slave alternate with generating the signal. As master and slave share the line, there is an urgent need to use “open drain” instead of usual “push-pull” in order to avoid shorts. I2C is slightly more complex to implement in hardware compared to SPI; although, it is very easy to implement in software by bit-banging the GPIOs. Typically, I2C uses 7-bit addresses, so that - minus eight reserved addresses - 120 slave devices could be connected to a single I2C bus. Apart from the start and stop sequence, data are always transferred in bytes. When the slave address is sent, the eighth bit is a “read/write” bit that determines if data are written to or read from the slave afterwards. After each transmitted byte, the reading device confirms the received data and the continuation of the transfer with an “ack/nack” bit. Today, a transmission rate of 400 kHz is common and a rate of 5 MHz is possible, so that I2C is suitable for many applications where only slower, half-duplex or occasional transfers are required. Besides 7-bit addresses, also 8-bit and 10-bit addresses may be used so that the number of slave devices can be even greater. Some manufacturers refrain addresses entirely, as for example Sensirion did with its SHT1x humidity and temperature sensor IC. Ultimately, the focus on the following pages will be on 7-bit addresses.
System Management Bus
SMBus is a two-wired bus for synchronous communication based on I2C. It allows a clock rate between 10 and 100 kHz. Furthermore, it has a clock low timeout mode, which means that a device can abort a transfer in progress. The master sends a stop condition and the slaves must reset their communication and wait for a new start condition. Therefore, a minimum of 25 ms and a maximum timeout value of 35 ms are specified. This timing parameters, however, are not specified in I2C.
Controller Area Network
CAN is an asynchronous bus-based serial communication protocol providing half-duplex communication among microcontroller boards and other devices. It is working according to the multi-master principle meaning that there are several nodes, which can initiate transactions. These nodes are connected to each other through a two-wire bus. The advantage of CAN is the ability of error detection and repair.
I2S is a synchronous serial communication protocol for the audio transfer between a variable number of devices. Usually there are two lines, the “Serial Data (SD)” and “Word Select (WS)” line, besides the implied “Serial Clock (SCK)” lines.
Universal Serial Bus
USB is also a serial bus interface using two wires for power and two for differential data signals for half-duplex data transfer (USB 2.0), and additional four wires for full-duplex super speed (USB 3.0). It allows communication between a computer and external devices. However, it is not designed for intra-board communication and therefore not further described here.